COMPUTER Organization:ALU and DataPath

​The CPU can be divided into a data section and a control section. The data section, which is also called the datapath.

Datapath

The registers, the ALU, and the interconnecting bus are collectively referred to as the datapath. Each bit in datapath is functionally identical. The datapath is capable of performing certain operations on data items.

The control section is basically the control unit, which issues control signals to the datapath.

Bus: A Bus is a collection of wires or distinct lines meant to carry data, address and control information.

Data Bus: it is used for transmission of data. The number of data lines corresponds to the number of bits in a word.

Address Bus: it carries the address of the main memory location from where the data can be accessed.

Control Bus: it is used to indicate the direction of data transfer and to coordinate the timing of events during the transfer.

PC (Program Counter): Holds the address of the next instruction

IR (Instruction Register): Holds the executing instruction

Instruction Cache: ‘Fast’ memory where the next instruction comes from Reg[index]

(Register File): Contains the 32 registers

Arithmetic Logic Unit (ALU): Performs all arithmetic operations

Data Cache: Data read from or written to ‘fast’ memory

Multiplexer: Multiple inputs selects one output based upon control signal(s)

Single-Cycle Data Path: Each instruction executes in one clock cycle

Multi-Cycle Data Path: Each instruction takes multiple clock cycles

Single-Cycle Data Path:

  • Every cycle must be equal length
  • The cycle time must be long enough to accommodate the longest instruction.

Multi-cycle Data Path

  • Have the cycle time coincide with the instruction stage time.
  • Cycle time = 2 ns (time of longest stage)
  • Between stages we need registers to hold data for next stage.

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  • Accumulator: Special register
    • One of the inputs to ALU
    • Output of ALU stored back in accumulator
  • One-address instructions: Operation and address of one operand
    • Other operand and destination is accumulator register
    • AC <– AC op Mem[addr]
    • Single address instructions (AC implicit operand)
  • Multiple registers: Part of instruction used to choose register operands

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Instruction Path

  • Program Counter
    • Keeps track of program execution
    • Address of next instruction to read from memory
    • May have auto-increment feature or use ALU
  • Instruction Register
    • Current instruction
    • Includes ALU operation and address of operand
    • Also holds target of jump instruction
    • Immediate operands
  • Relationship to Data Path
    • PC may be incremented through ALU
    • Contents of IR may also be required as input to ALU

Memory Interface

Memory

  • Separate data and instruction memory: Two address busses, two data busses
  • Single combined memory: Single address bus, single data bus

Separate memory

  • ALU output goes to data memory input
  • Register input from data memory output
  • Data memory address from instruction register
  • Instruction register from instruction memory output
  • Instruction memory address from program counter

Single memory

  • Address from PC or IR
  • Memory output to instruction and data registers
  • Memory input from ALU output

One-Bus Organization

  • CPU registers and the ALU use a single bus to move outgoing and incoming data.
  • Bus can handle only a single data movement within one clock cycle.
  • This bus organization is the simplest and least expensive.
  • It limits the amount of data transfer that can be done in the same clock cycle, which will slow down the overall performance.

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Two-Bus Organization

  • General-purpose registers are connected to both buses.
  • Data can be transferred from two different registers to the input point of the ALU at the same time.
  • Two operand operation can fetch both operands in the same clock cycle.

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Three-Bus Organization

  • Two buses may be used as source buses while the third is used as destination.
  • The source buses move data out of registers (out-bus), and the destination bus may move data into a register (in-bus).
  • Each of the two out-buses is connected to an ALU input point. The output of the ALU is connected directly to the in-bus
  • Increasing the number of buses will also increase the complexity of the hardware.

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INSTRUCTION CYCLE

  • The sequence of operations performed by the CPU during its execution of instructions.
  • At the completion of the instruction execution, a test is made to determine whether an interrupt has occurred.
  • An interrupt handling routine needs to be invoked in case of an interrupt.

The basic actions during fetching an instruction, executing an instruction, or handling an interrupt are defined by a sequence of micro-operations.

A group of control signals must be enabled in a prescribed sequence to trigger the execution of a microoperation.

Condition Codes: The processor keeps track of some information about the results of various operations for use by subsequent conditional branch instructions, by recording the required information into individual bits called as condition code flags. Some processors may collect this information in Status register or condition code register.

Important flags of status/condition code register:

  • N (negative) Sets to 1 if the result is negative; otherwise, cleared to 0
  • Z (zero) Sets to 1 if the result is 0; otherwise, cleared to 0
  • V (overflow) Sets to 1 if arithmetic overflow occurs; otherwise, cleared to 0
  • C (carry) Sets to 1 if carry-out results from the operation; otherwise, cleared to 0